
Timer Interface Module (TIM)
MC68HC908QY/QT Family Data Sheet, Rev. 6
128
Freescale Semiconductor
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as a 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTA2/TCLK pin or one of the seven prescaler outputs as the
input to the TIM counter as
Table 14-2 shows. Reset clears the PS[2:0] bits.
14.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Table 14-2. Prescaler Selection
PS2
PS1
PS0
TIM Clock Source
0
Internal bus clock ÷ 1
0
1
Internal bus clock ÷ 2
0
1
0
Internal bus clock ÷ 4
0
1
Internal bus clock ÷ 8
1
0
Internal bus clock ÷ 16
1
0
1
Internal bus clock ÷ 32
1
0
Internal bus clock ÷ 64
11
1
PTA2/TCLK
Address: $0021
TCNTH
Bit 7
654321
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
00000000
Address: $0022
TCNTL
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
00000000
= Unimplemented
Figure 14-5. TIM Counter Registers (TCNTH:TCNTL)