
110
32000D–04/2011
AVR32
9.3.5
Logic Operations
Table 9-5.
Logic Operations
Mnemonics
Operands / Syntax
Description
Operation
Rev
and
CRd, Rs
Logical AND.
Rd
← Rd ∧ Rs
1
E
Rd, Rx, Ry << sa
Rd
← Rx ∧ (Ry << sa5)
1
E
Rd, Rx, Ry >> sa
Rd
← Rx ∧ (Ry >> sa5)
1
and{cond4}
E
Rd, Rx, Ry
Logical AND if condition satisfied.
if (cond4) Rd
← Rx ∧ Ry
2
andn
C
Rd, Rs
Logical AND NOT.
Rd
← Rd ∧ Rs
1
andh
ERd, imm
Logical AND High Halfword, low halfword is
unchanged.
Rd[31:16]
← Rd[31:16] ∧ imm16
1
E
Rd, imm, COH
Logical AND High Halfword, clear other
halfword.
Rd[31:16]
← Rd[31:16] ∧ imm16
Rd[15:0]
← 0
1
andl
ERd, imm
Logical AND Low Halfword, high halfword
is unchanged.
Rd[15:0]
← Rd[15:0] ∧ imm16
1
E
Rd, imm, COH
Logical AND Low Halfword, clear other
halfword.
Rd[15:0]
← Rd[15:0] ∧ imm16
Rd[31:16]
← 0
1
com
C
Rd
One’s Complement (NOT).
Rd
← Rd
1
eor
CRd, Rs
Logical Exclusive OR.
Rd
← Rd ⊕ Rs
1
E
Rd, Rx, Ry << sa
Rd
← Rd ⊕ (Rs << sa5)
1
E
Rd, Rx, Ry >> sa
Rd
← Rd ⊕ (Rs >> sa5)
1
eor{cond4}
E
Rd, Rx, Ry
Logical EOR if condition satisfied.
if (cond4) Rd
← Rx ⊕ Ry
2
eorh
E
Rd, imm
Logical Exclusive OR
(High Halfword).
Rd[31:16]
← Rd[31:16] ⊕ imm16
1
eorl
E
Rd, imm
Logical Exclusive OR
(Low Halfword).
Rd[15:0]
← Rd[15:0] ⊕ imm16
1
or
CRd, Rs
Logical (Inclusive) OR.
Rd
← Rd ∨ Rs
1
E
Rd, Rx, Ry << sa
Rd
← Rd ∨ (Rs << sa5)
1
E
Rd, Rx, Ry >> sa
Rd
← Rd ∨ (Rs >> sa5)
1
or{cond4}
E
Rd, Rx, Ry
Logical OR if condition satisfied.
if (cond4) Rd
← Rx ∨ Ry
2
orh
E
Rd, imm
Logical OR (High Halfword).
Rd[31:16]
← Rd[31:16] ∨ imm16
1
orl
E
Rd, imm
Logical OR (Low Halfword).
Rd[15:0]
← Rd[15:0] ∨ imm16
1
tst
C
Rd, Rs
Test register for zero.
Rd
∧ Rs
1