參數(shù)資料
型號： PSD411A1-C-15U
廠商： 意法半導(dǎo)體
英文描述： High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125
中文描述： 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù)： 54/123頁
文件大?。?/td> 657K
代理商： PSD411A1-C-15U
PSD4XX Famly
51
Register Name
Port
Write/Read
Control Register
A,B,C,D,E
Write/Read
Direction Register
A,B,C,D,E
Write/Read
Open Drain Register
C,D
Write/Read
PLD – I/O Register
A,B,E
Read
Table 13. Port Configuration Registers (PCR)
Register Name
Port
Read/Write
Data In Register
A,B,C,D,E
Read
Data Out Register
A,B,C,D,E
Write/Read
Macrocell Out Register
A,B,E
Read
Table 14. Port Data Registers (PDR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7 Pin
PA6 Pin
PA5 Pin
PA4 Pin
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
Table 15.
Data In Register – Port A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7 Pin
PA6 Pin
PA5 Pin
PA4 Pin
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
= 0
= 0
= 0
= 0
= 0
= 1
= 1
= 1
Drection Register – Port A
(Example: Pins PA0 – PA2 as Output, PA3 – PA7 as Input)
9.3.9 Port Registers
There are two sets of registers per I/O port: the Port Configuration Registers (PCR) which
consist of four 8-bit registers; and the Port Data Registers (PDR) which include three 8-bit
registers. The PCR is used for setting up the port configuration, while the PDR enables the
microcontroller to write or read port data or status bits. Tables 13 and 14 show the names
and the registers and the ports to which they belong.
All the registers in the PCR and PDR are 8-bits wide and each bit is associated with a
pin in the I/O port. In Table 15, the LSB of the Data In Register of Port A is connected to
pin PA0, and the MSB is connected to PA7. This pin configuration also applies to other
registers and ports. For example, in the Direction Register of Port A, writing a hex value of
07 to the register configures pins PA0 – PA2 as output pins, while PA3 – PA7 remain as
input pins.
Registers can be accessed by the microcontroller during normal read/write bus cycles.
The I/O address offset of the registers are listed in the System Configuration section.
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料
PDF描述
PSD411A1-C-70J High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125
PSD411A1-C-70L High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125
PSD411A1-C-70U High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125
PSD411A1-C-90JI High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125
PSD411A1-C-90UI High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-PDIP -55 to 125
相關(guān)代理商/技術(shù)參數(shù)
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PSD411A1-C-70L 制造商:WSI 功能描述:
PSD411A1-C-70U 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD411A1-C-90JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
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