參數(shù)資料
型號(hào)： S1C88409D
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108
封裝： DIE-108
文件頁(yè)數(shù)： 48/250頁(yè)
文件大小： 1877K
代理商： S1C88409D
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S1C88409 TECHNICAL MANUAL
EPSON
131
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
5.14.2 Transfer mode
and input/output terminals
In this serial interface, the transfer mode can be
selected by software.
Transfer mode summary
Clock synchronous transfer is the formula that
transfers 8-bit data by synchronizing each bit to a
clock common to transmitter and receiver.
Asynchronous transfer is the formula that trans-
fers the serial converted data in which a start bit is
added to the front and a stop bit is added to the
rear. In this formula, it is not necessary to use the
same synchronous clock for transmitter and
receiver. Data transfer is done by synchronizing
the start/stop bit attached in front and rear of each
data. The asynchronous interface has separate
transmit and receive shift registers and is designed
to permit full duplex transmission to be done
simultaneously for transmitting and receiving.
Four transfer modes shown below are available in
this interface.
(1) Clock synchronous master mode
In this mode, clock synchronous 8-bit serial
data transfer can be done. This serial interface
becomes the master and uses the internal clock
as the synchronous clock for the built-in shift
register.
The synchronous clock is output from the
SCLK terminal and can control the external
serial I/O device (the slave side).
Figure 5.14.2.1 shows a connection example of
input/output terminals in clock synchronous
master mode.
Data input
Data output
CLOCK input
READY output
SIN (P10/P14)
SOUT (P11/P15)
SCLK (P12/P16)
Input port (Kxx)
External
serial device
S1C88409
Fig. 5.14.2.1 Connection example of clock synchronous
master mode
(2) Clock synchronous slave mode
In this mode, clock synchronous 8-bit serial
data transfer can be done. This serial interface
becomes the slave and uses the synchronous
clock supplied externally (the master side).
The synchronous clock is input from the SCLK
terminal and is used in this serial interface.
Further, this mode can output the SRDY signal
that indicates transmit/receive ready status
from the SRDY terminal.
Figure 5.14.2.2 shows a connection example of
input/output terminals in clock synchronous
slave mode.
Data input
Data output
CLOCK output
READY input
SIN (P10/P14)
SOUT (P11/P15)
SCLK (P12/P16)
SRDY (P13/P17)
External
serial device
S1C88409
Fig. 5.14.2.2 Connection example of clock synchronous
slave mode
(3) 7-bit asynchronous mode
In this mode, start stop synchronous transfer
can be done. Data length is 7 bits. It is possible
to select a stop bit length, addition of a parity
bit and even/odd parity.
Further, this mode works only with the internal
clock.
Figure 5.14.2.3 shows a connection example of
input/output terminals in asynchronous mode.
(4) 8-bit asynchronous mode
In this mode, start stop synchronous transfer
can be done. Data length is 8 bits. It is possible
to select a stop bit length, addition of a parity
bit and even/odd parity.
Further, this mode works only with the internal
clock.
Figure 5.14.2.3 shows a connection example of
input/output terminals in asynchronous mode.
Data input
Data output
SIN (P10/P14)
SOUT (P11/P15)
External
serial device
S1C88409
Fig. 5.14.2.3 Connection example of clock
asynchronous mode
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