
Page 142
Epson Research and Development
Vancouver Design Center
S1D13A05
Hardware Functional Specification
X40A-A-001-02
Issue Date: 02/07/02
bits 9-8
Source Driver IC Number Bits [1:0]
These bits contain the number of Source Driver ICs.
bit 0
Command Send Request
After the CPU sets this bit, the S1D13A05 sends the command in the next non-display
period and clears this bit automatically. This register has no effect for all other panel inter-
faces.
Type 3 TFT Miscellaneous Register
REG[F8h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
Source Driver IC
Number bits 1-0
n/a
Command
Send
Request
15
14
13
12
11
10
9
8
7
6
5
4
3
2
10
Table 8-33: Number of Source Driver ICs
REG[E0h] bits 1-0
Source Driver ICs
00
1
01
2
10
3
11
4