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| 型號： | TMS320WP010PZA |
| 英文描述： | Cell-Phone Circuit |
| 中文描述： | 手機電路 |
| 文件頁數(shù)： | 51/132頁 |
| 文件大?。?/td> | 1707K |
| 代理商： | TMS320WP010PZA |
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
input qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP1
–
6, XINT1/2, ADCSOC and PDPINTA/B pins
in the 240xA devices. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the
internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch
smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin
high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls
whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches. On the
LC2402A, input qualification is for the CAP1, CAP2, CAP3, PDPINTA, and XINT2/ADCSOC pins.
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 11. The ADC module consists of
a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
10-bit ADC core with built-in S/H
16-channel, muxed inputs
Autosequencing capability provides up to 16
“
autoconversions
”
in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
–
The digital value of the input analog voltage is derived by:
Digital Value
1023
Input Analog Voltage
V
REFHI
V
REFLO
V
REFLO
Multiple triggers as sources for the start-of-conversion (SOC) sequence
–
S/W
–
software immediate start
–
EVA
–
Event manager A (multiple event sources within EVA)
–
EVB
–
Event manager B (multiple event sources within EVB)
–
Ext
–
External pin (ADCSOC)
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in
“
start/stop
”
mode, allowing multiple
“
time-sequenced triggers
”
to synchronize
conversions
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
NOTE: The calibration and self-test features are not present in 240xA devices.
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